Gennum's Snowbush IP Group Offers SATA/ SAS IP Block

Shortening the development time and risk associated with system-on-chip (SoC) design for high- performance computing, Gennum Corporation has announced that its Snowbush IP group has developed a Serial Advanced Technology Attachment (SATA) 6 gigabits per second (Gb/s) physical layer (PHY) intellectual property (IP) block. The new IP also satisfies the requirements of the latest Serial Attached SCSI (SAS) standard, SAS 2.0 (SAS-2). The SATA/SAS IP is being offered for manufacture in a variety of 65-nm and 45-/40-nm processes, including TSMC, as well as Common Platform Alliance members IBM, Chartered and Samsung.

The industry is undergoing a rapid transition to the higher data rates delivered by the Serial ATA International Organisation: Serial ATA Revision 3.0 and SAS-2 standards. SATA and SAS are technologies used to transfer data to and from mass storage devices, such as hard disk drives and optical drives. The new SATA/ SAS PHY IP has been optimised to deliver a low-power solution with a small silicon footprint that meets the requirements of both the SATA 6 Gb/s and SAS-2 specifications, while providing designers the margin they need to deliver a manufacturable design. By eliminating the need for companies to develop complex PHY technology in-house, Gennum can shorten the development cycle by as much as a year.

More from Biztech

Future Group - Reliance Retail Deal approved by CCI RBI ban on cryptocurrencies takes effect; prohibition could force investors to tap the black market

“As storage standards evolve, our customers must be able to support the latest data rates without the significant investment and risk that typically accompany high-speed PHY development,” said Ewald Liess, general manager of the Snowbush IP group for Gennum. “We have developed and verified one of the most complex interface functions for mass storage devices, enabling customers to reduce the time and resources associated with in-house development, while at the same time helping them meet their goal of achieving first-pass silicon success with a power- and area-efficient solution.”