Intel Foveros: A new 3D chip stacking technology to help Intel regain lost ground to TSMC

**Intel** said on 12 December that it has developed a way to stack its computing circuits on top of one another in a bid to regain the lead in chip manufacturing technology that it has lost to rivals like **Taiwan Semiconductor** in recent years. Intel, the world’s biggest maker of computing chips for personal computers and data centres, for decades followed Moore’s law, named for company co-founder Gordon Moore, by doubling the number of transistors on a chip every two years, thus roughly doubling their performance. But as those transistors have shrunk to just a few nanometers apart, the company has fallen years behind schedule on its own plans. The company said in July that chips featuring its newest 10-nanometer manufacturing technology will not arrive until the holiday shopping season of 2019. [caption id=“attachment_5721731” align=“alignnone” width=“1280”] Raja Koduri, Intel chief architect, senior vice president of Core and Visual Computing Group and general manager of Edge Computing Solutions. Image: Intel Corporation[/caption] In the meantime, most of Intel’s biggest rivals such as **Nvidia** and **Qualcomm** long ago quit manufacturing chips and outsourced the work to firms like TSMC. The Taiwanese firm rolled out its **newest generation of chipmaking technology** this year and snatched away the company’s title of making the tiniest chips.

Intel Foveros: What is it?

But Intel said it now has the technology to stack computing circuits on top of each other and wire them together with speedy connections, enabling it to pack more onto a single chip. Stacking has been used in memory chips before, with AMD’s **High Bandwidth Memory** , but Intel would be the first company to successfully stack the so-called “logic” chips that handle computing tasks, Raja Koduri, Intel’s chief of chip architecture, told Reuters in an interview. [caption id=“attachment_5723081” align=“alignnone” width=“1280”].jpg) Intel Foveros. Image: Intel[/caption] “We’ve been working on this packaging technology for nearly 20 years,” Koduri said. “There’s some real physics problems to solve in stacking logic on logic.” The stacking technology will be available in the second half of next year, Intel said. It will also let Intel break up its chip designs into smaller units called “chiplets” so that, for example, memory and computing chips can be stacked in different combinations. The manufacturing technology, called Foveros, is expected to help Intel boost the performance of chips from processors to those used specifically for artificial intelligence (AI) tasks. In a way, Foveros helps Intel find a way around Moore’s Law, which has been reaching its limits over the years. Intel rival TSMC has already moved on to the 7 nm manufacturing process and we are already seeing chipsets based on the 7 nm designs making their way into smartphones. According to Intel, new insulation materials which dissipate heat faster and new power-delivery processes have helped it overcome the limitations that one would generally face when stacking processor cores on top of each other. Foveros tech not only helps boost processing power on chipsets but is also expected to make it easier to change transistors for specific use cases. [caption id=“attachment_5722991” align=“alignnone” width=“1280”] Intel Foveros will incorporate vertical 3D chip integration on the same die. Image: Intel[/caption] According to a report in Ars Technica, the first Foveros-based products would comprise a chip built on a 10nm process stacked atop a base die using Intel’s 22FFL (FinFET low power) process. The 10nm part will house the high power Sunny Cove core and four low power Atom cores — analogous to the big.LITTLE architecture we see on ARM processors where a set of processors perform high-end tasks and another set performs low power tasks. This chip is expected to be targetted at ultra-mobile systems which the processor measuring 12 x 12 x 1 mm and with a standby power of 2mW

Intel Foveros: Challenges

The major challenge with making vertically stacked processor core sporting chips would be to manufacture them at scale and across power profiles. According to chip industry analyst Linley Gwennap, this approach should work well for low-power processors, but he’s sceptical that this process would work for high-power chips for desktops and server processors. Koduri said that will let Intel meet changing customer needs instead of selling “monolithic” chips. But Jack Gold, an analyst with J Gold Associates, said the technology will also help Intel move faster against rivals like Advanced Micro Devices which are using TSMC’s technology. While computing chips get a speed boost after being shrunk, many other kinds of chips do not and can work well when made with older technology. Intel will be able to use those old elements with its newest computing circuits without having to redesign them, Gold said. “They’re going to be able to stack new chips and old chips together to get to market faster,” he said. With inputs from Reuters