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ASIC Verification Methodology With TotalRecall

Minu Sirsalewala December 23, 2014, 18:53:34 IST

Synplicity, a supplier of software for the design and verification of semiconductors, recently released details on its TotalRecall Full Visibility Technology. Synplicity believes that this new technology will dramatically improve the utility of FPGA prototypes as ASIC verification vehicles by giving designers the ability to rapidly find bugs and verify that the correct fix has been made. The TotalRecall technology allows access to debug visibility that meets or exceeds that of an emulator, while running at speeds of 10x to 100x faster.

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ASIC Verification Methodology With TotalRecall

Synplicity, a supplier of software for the design and verification of semiconductors, recently released details on its TotalRecall Full Visibility Technology. Synplicity believes that this new technology will dramatically improve the utility of FPGA prototypes as ASIC verification vehicles by giving designers the ability to rapidly find bugs and verify that the correct fix has been made.

The TotalRecall technology allows access to debug visibility that meets or exceeds that of an emulator, while running at speeds of 10x to 100x faster. This technology enables the capture of full signal information leading up to an event, as well as after the event occurs.

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The TotalRecall technology allows the capture of all the signals within a design (either a module or the full chip), including memory states, a user-defined number of cycles prior to the point at which an error occurs. The complete design state, along with an automatically generated test bench, can then be exported to an HDL simulator where the sequence can be replayed as many times as necessary until the problem is understood and a fix verified.

The TotalRecall technology also supports hardware verification techniques enabled by the use of assertions synthesized into hardware. Many IC designers use assertions in the design flow but do not fully utilize them for verification due to their slow simulation speeds.

“TotalRecall technology is an exciting step forward in debug visibility and productivity,” stated Gary Meyers, president and CEO, Synplicity. “Combined with the already high performance and low cost of FPGA prototypes, the new capabilities of the TotalRecall technology will position prototypes as the leading method for ASIC verification.”

The TotalRecall technology works for non-deterministic bugs found in live running hardware. For this class of bugs, and other rarely occurring bugs, it is almost impossible to verify that changes made to the RTL code have truly fixed a bug.

Synplicity sees opportunity for its TotalRecall technology to be well integrated with capabilities from outside partners, particularly members of its Partners in Prototyping program. Synplicity will be developing reference design flows and integration with all major simulation environments.

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