Altera's Full-Compliance Support For FPGAs Announced

Altera has announced their full-compliance support for high-performance DDR3 memory interfaces. Under the newly ratified JESD79-3 JEDEC DDR3 SDRAM Standard, Altera’s Stratix III family of FPGAs reportedly provides designers with high-performance and low-power benefits of DDR3 memory.

The release states that Stratix III FPGAs support, read and write leveling functionality embedded directly into the I/O element. This helps ensure compliance with the JEDEC write leveling requirement and corrects alignment of data reaching the FPGA fabric.

Louie Leung, Altera’s marketing director said, “Our customers will now be able to quickly take advantage of the performance improvements in DDR3.”

Stratix III FPGAs offer support for the DDR3 SDRAM high-speed external memory interface on up to 1,104 user I/O pins arranged in 24 modular I/O banks with DQS logic on all I/O banks and 31 embedded registers per I/O for maximum DDR3 performance. Stratix III devices reportedly support DDR3 with a maximum clock speed of 400 MHz and maximum data rate of 800 Mbps.